Memory systems may employ a plurality of clock signals, including a write clock signal and a system clock signal. The memory system may issue write data signals to the memory device in accordance with the write clock and issue command and address signals to the memory device in accordance with the system clock. Referring to FIG. 1, a memory system 10 includes a controller 20. The controller issues write clock 22 and system clock 24 signals to the memory device 30 having 128 data inputs (DQs) 32a-h and command and address inputs (not shown). The write clock signal 22 is routed to the device 30 at a plurality of write clock inputs 34a-h, each local to a respective group of DQs 32a-h. 
The write clock signal 22 is issued to each DQ through local clock trees 36a-h. The memory system 10 of FIG. 1 includes a clock input for every 16 DQs and the device 30 includes 128 DQs, as shown. The system clock signal 24, however, is applied to the device 10 at a signal system clock input 40. The system clock signal 24 may be used throughout the memory device 30, for example, for clocking circuits to capture command and address signals in synchronicity with the system clock signal 24. While the system clock signal 24 may be used for a variety of functions on the memory device 20, the controller 20 issues address and command signals destined for the memory device 30 in accordance with the system clock signal 24. The system clock signal 24 is routed internally through a global clock tree 42 so that the system clock signal 24 can be used to synchronize various operations according to the system clock signal 24. The system clock signal 24 is also routed by the global clock tree 42 to each of the local clock trees 36a-h (connections not shown in FIG. 1 for simplicity).
Accordingly, write data signals are received in accordance with the write clock signal at each DQ 32a-h and command and address signals received in accordance with the system clock signal at the command and address inputs, respectively. For the memory device to accurately capture and match address signals with the correct corresponding write data, the write clock and system clocks should be in synch at the DQs and the address inputs. However, as shown in FIG. 1, the internal system and write clock paths may differ, and as a result, the system and write clocks would be out of synch by the time they reach the individual DQs 32a-h and address inputs. For example, the system clock experiences extra delay due, for example, to the global clock tree 42. Traditional systems ensure sufficient synchronization between the DQs and the address inputs by delaying the write clock signals an additional amount such that they are delayed by approximately the same amount as the system clock signal is delayed due to the different internal clock path.
As memory speeds continue to increase, however, the traditional method for ensuring write and system clock synchronization by delaying the write clock signal to match the system clock signal delay may fail. As clock speeds continue to increase, the delay from the system clock input 40 to the individual DQs 32a-h may be on the order of several clock periods. Furthermore, the delay experienced by the system clock signal will vary according to process, voltage and temperature conditions of the memory device 30.
Accordingly, simply delaying the write clock an additional amount to match a delay of the system clock may not suffice. For one thing, the process, voltage and temperature variation may not affect the delays in the same manner, continuing to contribute to a mismatch. Further, as the mismatch of delay increases to several clock periods, received data signals may be stored while waiting for receipt of the corresponding system clock signal. It may be difficult to know how much storage would be needed to accommodate the delay in receipt of the system clock signal. It is also difficult to match the received write data signals with the corresponding address signals that are received, routed and therefore delayed in the same manner as the system clock signal.
The problem is still further exacerbated because write data is captured at the frequency of the original write clock signal while the system clock may be internally divided by two on the memory device. Accordingly, phase control between the slower system clock and the faster write clock signal may be of increasing importance.
There is accordingly a need for a system of coupling write data and address signals to a memory device that accommodates the different routing of system clock and write clock signals such that the system clock and write clock signals are in synch and the correct address signals are matched with their corresponding write data.